The present invention relates to integrated circuit memory, and more specifically to an apparatus and method of controlling a read cycle of a gain cell type dynamic random access memory with an interlock signal.
For several decades, the one transistor dynamic random access memory (DRAM) has been the dominant choice for high-density and low-cost semiconductor memory in computing systems. Recently, advancements in miniaturization have allowed DRAM to be integrated or “embedded” into the same integrated circuit (“IC” or “chip”) as a processor which requires access to a memory. Embedding DRAM on the same chip with the processor not only reduces packaging cost, but also significantly increases available processor to memory bandwidth. Because of the smaller memory cell size, embedded DRAMs can be about three to six times denser than embedded static random access memories (SRAMs), and operate with lower power dissipation and up to 1000 times lower soft-error rate.
DRAMs which are embedded into chips having a processor function are typically implemented by a one transistor and one capacitor DRAM cell structure (1T1C cell), which is commonly used in standalone commodity DRAMs. FIG. 1a illustrates a transistor level schematic of a 1T1C DRAM cell 10A. When a wordline, e.g. WLA, of the DRAM is activated, the access transistor 11A coupled to that wordline turns on, which then couples the capacitor 12A having a voltage stored thereon to the bitline BLA. This results in a small voltage signal on BLA due to the transfer of charge from the capacitor 12A to BLA, or from BLA to the capacitor 12A depending on the value of the voltage stored on the capacitor. As a result of this charge transfer, the voltage on capacitor 12A that originally represented a data bit is destroyed, which is termed “destructive read”.
Bitline BLA and another bitline BLB of the DRAM form a pair of bitlines coupled to a sense amplifier 15. The other bitline BLB of the pair, is not coupled to a memory cell 10A accessed by the activated wordline WLA, but is instead coupled to a memory cell 10B which is only accessible by a different wordline WLB. Bitline BLB retains a bitline precharge voltage, and is used to provide a reference voltage to a sense amplifier 15. At the sense amplifier 15, the small voltage difference between BLA and BLB of the bitline pair is amplified to rail-to-rail logic levels. The amplified logic level signals on the bitline pair BLA, BLB are then available to be read out from the memory. If the particular column address corresponding to bitline BLA has been selected through column select line CSL, the signals on the bitline pair are transferred to a pair of data lines DLA and DLB.
Whether or not the particular bitline pair is selected for read out by CSL, a writeback operation must now be performed to restore the data to all the cells of the 1T1C DRAM that have been accessed by the activated WLA, the data having been destroyed as a result of accessing those cells by WLA. This is performed by the sense amplifier 15 driving the pair of bitlines BLA, BLB with the amplified logic levels that were obtained in the previous step. As a result of this operation, the accessed cells are restored with the same data that they held before being accessed.
Instead of writing back the previously stored information, another possible operation at this time is to write new information into the accessed cell coupled to the bitline BLA. In this operation, the sense amplifier 15 drives the voltages on the pair of bitlines BLA and BLB to complementary low and high levels, or high and low levels, respectively, according to write data signals that are input thereto from the data line pair DLA and DLB. Typically, the write operation is performed after a read operation, because only some selected cells of the many cells that are accessed by the activated wordline WLA are to be written in a given write operation, and the data stored in other cells accessed by the activated wordline WLA are destroyed as a consequence of accessing the cells, i.e., the write operation to a 1T1C DRAM is destructive. The sense amplifier 15 must then write back the accessed data bits of the nonselected cells in a writeback operation as described above, which is typically done simultaneously with the write operation to the selected cells. This process of simultaneously writing back stored data while writing new data to some cells is known as a read modified write operation.
In a 1T1C DRAM, the destructive read operation followed by write back, and the read modified write operation made necessary because of the destructive nature of writing, require longer cycle times than read and write operations performed within an SRAM because read and write operations are nondestructive in an SRAM. This makes the performance advantage of conventional embedded DRAMs small over standalone commodity DRAMs. Hence, the essential advantage of conventional embedded DRAMs up to the present time has been to provide high-capacity memory on the same chip as a processor, e.g., for executing graphics applications, rather than as a high density, high performance alternative to SRAM.
In order to increase the benefits of using embedded DRAM over standalone DRAM or other types of IC memory, improvements have been made to the architecture of embedded DRAMs to improve bandwidth, latency and cycle time. Because the width of the input output (I/O) interface between processor and embedded memory is already much larger than the I/O width to an external (off-chip) memory, page mode operation which is commonly used for standalone DRAMs does not greatly increase the average speed of accessing the embedded DRAM. Instead, improvements in the time to randomly access cells of the DRAM (a measure of latency) and the cycle time (a measure of address bandwidth) are paramount to increasing the performance of the embedded DRAM relative to alternative types of on-chip memory, e.g. SRAM, or standalone DRAM. However, as described above, the performance of a 1T1C DRAM is strongly dependent on the cycle time needed to write back previously stored information after reading cells or while writing to selected cells of the DRAM.
A particular type of DRAM known as “gain cell DRAM” exhibits much improved cycle time over conventional 1T1C DRAM, due to the nondestructive nature by which the gain cell DRAM is read and written. Accordingly, in a gain cell DRAM, the long duration read/writeback operation and read modify write operation of 1T1C DRAM are not needed, such that the cycle time for accessing cells of the gain cell DRAM is much improved.
FIG. 1b shows a schematic of a three transistor, one capacitor cell 10 of a gain cell DRAM (3T1C gain cell DRAM). Each gain cell 10 includes a capacitor 21 for storing a voltage representing a data bit, a write access transistor 20C coupled to a write wordline WWL for storing a voltage on the capacitor 21 from a write bitline WBL, and a state transistor 20B having a gate coupled to the capacitor 21 for indicating the stored state on the capacitor 21 over many read operations performed after the voltage has been stored on the capacitor 21. The gain cell 10 also includes a read access transistor 20A coupled to a read wordline RWL for outputting the current high voltage or low voltage state of the state transistor 20B onto the read bitline RBL.
In operation, read access is provided by activating the read wordline RWL, which then couples the state transistor 20B to the read bitline RBL. Depending upon the voltage stored on the capacitor 21, which is the same voltage applied to the gate of state transistor 20B, the state transistor 20B will either be on or off. If the state transistor 20B is off, the read bitline RBL will exhibit a voltage at or near the supply voltage Vdd that is connected to RBL through resistor R10. That high voltage on RBL will be detected as a first stored data bit value, a “1”, by the sense amplifier 25. However, if the state transistor 20B is on, the voltage on RBL will be pulled down by the conductive path to ground through transistors 20A and 20B. The sense amplifier 25 will detect the lowered voltage at that time on RBL as a different stored data bit, a “0”, than for the higher RBL voltage, the “1”, that exists when the state transistor 20B is turned off.
A write operation is performed using a write wordline WWL and write bitline WBL that are separate from the read wordline RWL and read bitline RBL that are provided for reading the gain cell 10. Writing is performed by activating the write wordline WWL to turn on transistor 20C, and then storing a write voltage on capacitor 21 from the write bitline WBL. The signal on the WBL is single ended. When writing to the gain cell 10, write control circuitry 27 drives the voltage on the write bitline WBL to either a high level such as the supply voltage VDD or a low level such as ground, depending on the value of the data bit being written.
It is apparent from the foregoing that read operations to the gain cell are nondestructive, in that the voltage stored on the capacitor 21 remains after many operations of reading the cell, since there is no conductive path between the capacitor 21 and the read bitline RBL. The nondestructive nature of the read operation allows the read cycle time to be shortened compared to 1T1C DRAMs, because accessed memory cells no longer need to be written back after reading. Because the read cycle time is so much shorter than in 1T1C DRAMs, use of a 3T1C gain cell design for DRAMs embedded into chips requiring fast access and low latency appears especially advantageous.
While the foregoing discussion indicates that gain cell DRAM may be an advantageous alternative to 1T1C DRAM, it would be desirable to further improve the cycle time and latency of gain cell DRAMs. In such way, gain cell DRAM can be an advantageous alternative to 1T1C DRAMs and/or SRAMs for embedding into chips having a processor function.